1. Field of the Invention
The invention relates to packages for integrated circuits, and more particularly to a leadframe or packaging substrate having individual bond fingers with alternate bonding areas.
2. Description of the Related Art
Integrated circuits (ICs) have become essential components of many consumer and commercial electronic products produced today, often replacing large numbers of discrete components and providing enhanced functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can often be reduced to a single integrated circuit. Continually shrinking device geometries and corresponding advances in circuit density have resulted in reduced core sizes for such integrated circuits. However, various packaging limitations have prevented a corresponding reduction in the size of I/O pad circuitry.
FIG. 1 shows various components of a semiconductor device package according to the prior art. A typical packaged integrated circuit contains many components. Individual, unpackaged integrated circuits are often referred to as a semiconductor "die" 100. A "leadframe" L is a sheet metal or similar framework upon which the semiconductor die 100 is attached, wire-bonded, and transfer molded with resin 101 or similar material to form the packaged semiconductor device. The leads of the leadframe L include sections referred to as "external leads" (not shown) that connect the finished device package to external circuitry such as a printed circuit board.
"Internal leads" or bond fingers 102 are sections of the leads in a leadframe that are inside the package body outline. More precisely, the term "bond finger" relates to an end portion of an internal lead that includes a "bonding area" 108. Very small diameter bonding wires 104 (usually formed of aluminum or gold) are attached between "bond pads" 106 on a semiconductor die 100 and the leadframe L. In a typical leadframe L, the external leads are individually electrically coupled with the bond fingers 102 and are formed from an unbroken section of conductive material to remove the need for lead clamping and to provide structural support during the packaging process.
The bonding area (also referred to as a "lead flat surface") 108 is generally wider than the nominal width of the elongated bond finger 102 and delineates the desired area of the bond finger 102 for wire bonding. The bonding area 108 may be specified as a percentage of the nominal bond finger 102 width for a specified length for both stamped and etched leadframes L. To provide a flat surface for bonding, the bonding area 108 of the bond finger 102 is often coined or flattened with a punch if the leadframe L is stamped, and may be plated with nickel or gold. As shown in FIG. 1, the bond fingers 102 approach the semiconductor die 100 within the semiconductor device package in a generally radial ("fan-in") pattern, or in parallel ranks approaching one or more edges 100a of the semiconductor die 100.
The term bond pad (or "bonding pad") 106 refers herein to a relatively large metallic area positioned on a planar surface of the semiconductor die 100. Bond pads 106 function to provide electrical contact between the semiconductor die 100 and the leadframe L via the bond wires 104 or "solder bump" (micro-bump) connections. Bond pads 106 are commonly incorporated in layout structures known as "pad cells" (not separately illustrated). The pad cells are typically disposed in rows about the periphery of the semiconductor die 100 in a ring-shaped area on the surface of the die between the edges 100a of the semiconductor die 100 and a core logic region 110. In addition to the bond pad 106, pad cells customarily include electrostatic discharge (ESD) protection circuitry and I/O circuitry such as pad drivers, slew rate control circuitry, and current spike suppression logic.
Often, the leadframe L is held together by sacrificial "bridges" between the external leads, which are removed after the leadframe L is bonded to the semiconductor die 100 and a package body is formed. The external leads then effectively provide separate electrical signal lines to the bond pads 106 of the semiconductor die 100. Following packaging of the assembly of FIG. 1 via a plastic molding process or other means, the external leads are singulated and individual pins are formed to provide electrical coupling to external circuitry.
Packaging substrates other than the traditional leadframe have also been developed, such as those used in ball-grid arrays (BGAs). Essentially, a BGA is an integrated circuit surface mount package with an array of solder balls that are attached to the bottom side of a thin, patterned substrate with conductive routing layers that include areas similar to the disclosed bond fingers 102. The solder balls are typically formed via a reflow process, while the semiconductor die 100 may be attached to the substrate using wire bonding or "flip-chip" interconnection.
Bond pads 106 and the associated pad cell circuitry are often variable in terms of pitch and size. The pitch is typically defined as a repeated distance between adjacent bond pads 106. Minimum bond pad pitch is limited by a number of factors, including minimum bond wire 104 width and the space temporarily occupied by the tool used to deposit the bond wires 104.
One reason for placing bond pads 106 around the periphery of the semiconductor die 100 is that such placement permits a large number of I/O connections to the semiconductor die 100 without unnecessarily long or crossing bond wires 104. However, bond pad pitch is often a limiting factor in the reduction of semiconductor die 100 size, particularly in integrated circuit designs that are I/O intensive. Such designs are often "pad-limited" (i.e., the size of the semiconductor die 100 is significantly greater than the size of the core logic region 110 due to the periphery space required to accommodate the rows of bond pads 106). Thus, appreciable gains in the utilization of the expensive silicon area in such designs can often be realized by reducing the pitch of the bond pads 106.
Bond pad pitch and associated packaging concerns are sometimes addressed by using special bonding techniques, such as "wedge-wedge" bonding (utilizing wedge shaped bonding pads) and "double-tier" bonding. These special bonding techniques are generally only available in expensive packages like pin grid arrays (PGAs) and are not suitable for use in mainstream plastic packages that are based on leadframes with a single tier of bonding fingers.
Also, a number of packaging technologies exist that permit reduced bond pad pitches, such as "flip-chip" (wherein connections are made to bump contacts covered with a conductive bonding agent on the face of a hybrid circuit) and tape automated bonding (TAB). Again, however, such techniques increase the cost and complexity of the packaging process.
In order to reduce bond pad pitch, semiconductor manufacturers have also created "staggered" bond pads 106, such as those illustrated in FIG. 1. In a staggered bonding approach, two staggered and substantially parallel rows of bond pads 106 are provided rather than a more conventional single row, in-line arrangement. The bond pads 106 of the outer row (closer to an edge 100a) are offset from the bond pads 106 of the inner row. As shown in FIG. 1, by similarly staggering the bonding areas of the bond fingers 102 effective bond pad pitch can be reduced while accounting for the aforementioned packaging and bonding limitations. Thus, a larger number of bond pads 106 may be accommodated in a given semiconductor die 100 area than could be accommodated by using single row, linear configuration of bond pads, and the occurrence of pad-limited designs is reduced.
Under certain circumstances, however, the staggered bonding areas of these leadframes or packaging substrates may actually necessitate an increase in the size of the semiconductor die 100. This is due in large part to the rigid nature of present staggered bonding approaches and associated manufacturing rules, in which the inner row (closer to core logic region 110) of bond pads 106 is required to be bonded to "outer" bonding areas 108 and bond pads 106 in the outer row are required to be bonded to inner bonding areas 108, as shown in FIG. 1. By allowing only a fixed number of bonding areas 108 in the inner and the outer rows of bonding areas of a leadframe L, it is often difficult to address variations in the configuration of bond pads 106 or pin ordering requirements without growing the size of the semiconductor die 100 to match the staggered pattern of the bonding areas 108.